ASML teams up with chip giants to roll out larger High‑NA EUV tools for data‑center chips

ASML, the Dutch maker of the world’s most advanced chip‑making machines, has just confirmed a big step forward for the industry – it will start working with its biggest customers to fit larger masks onto its upcoming High‑NA EUV tools. The idea is simple enough: a bigger mask lets the scanner print a bigger wafer area, and that, in turn, opens the door for the massive chips that power today’s AI servers and future data‑centre workloads.

Right now, the company’s current EUV tools can handle wafers up to about 800 mm², which is already at the upper edge of what chip designers like Nvidia, Google and others are asking for. The new High‑NA generation, which promises finer feature‑sizes, is limited by the size of the mask it uses – it’s a little too small to cover the really big chips that will dominate the market in the next decade.

Enter the 12‑inch (300‑mm) mask. By moving to a larger photomask, ASML says its High‑NA scanners will be able to print chips that are as big as the biggest data‑centre dies today, and even a bit bigger. The company is aiming to showcase a pilot production line using these larger masks by 2031, with the technology ready for high‑volume manufacturing around 2033.

Intel is already using the current generation of High‑NA tools for its laptop‑class processors, but the bigger masks are targeted at the high‑volume side of the market – think TSMC and Samsung’s advanced‑node fabs, as well as SK Hynix’s DRAM lines. SK Hynix, for its part, said it is weighing participation in a consortium around the 12‑inch mask and hopes to bring High‑NA EUV into DRAM mass‑production by 2028. TSMC expects to roll out High‑NA for high‑volume advanced‑node chips by 2030, while Samsung is eyeing the same for its DRAM products by 2028.

“If we’re going to pull it off as an industry, you’ll actually see the productivity of those systems go up by about 40 %,” said Marco Pieters, ASML’s chief technology officer, to Reuters. That boost would be a game‑changer, especially as AI models grow ever larger and the demand for wider, faster chips skyrockets.

In short, the move to larger masks could be the missing link that lets the semiconductor ecosystem keep pace with the relentless appetite for compute power. It’s a collaborative effort – ASML, the chipmakers, and the broader ecosystem will need to align on mask design, supply‑chain logistics and fab upgrades – but the payoff could be a new generation of chips that finally break the size ceiling we’ve been nudging against for years.